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Guild: wafer.space Community
Channel: 📐 - Designing / 🕰️-analog
After: 2025-10-31 11:59 p.m.
Before: 2025-12-01 12:00 a.m.
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[2025-11-01 3:58 a.m.] _.social._
hi there. anyone down to talk about silicon production (analog chips) in older processes? i'm talking to a fab and they're telling me the kind of design that i am talking to them about could result in a bunch of crosstalk, so i'm looking for ideas on how to mitigate that. the chip carries analog audio, so this is about capacitive coupling.


[2025-11-04 1:00 a.m.] mithro_
I would just do a tapeout with Tiny Tapeout and see if it matches expectations


[2025-11-04 1:01 a.m.] _.social._
tiny tapeout is great, but my ultimate goal is to go into commercial production with a fab


[2025-11-04 1:02 a.m.] _.social._
however, i resolved the crosstalk issue. i guess it was a translation problem between russian and english.


[2025-11-04 1:02 a.m.] _.social._
they didn't mean to say it was going to create a bunch of crosstalk, they were telling me they had a solution which has low cross talk.


[2025-11-04 1:02 a.m.] _.social._
they just didn't know how to say it 🙂


[2025-11-24 4:13 p.m.] 246tnt
So I'm trying to work on the power gates for TT but hitting some DRC errors. In particular `NP.12` I don't understand.


[2025-11-24 4:15 p.m.] 246tnt
`NP.12 : Overlap with P-channel poly2 gate extension is forbidden within 0.32um of P-channel gate.`

Which I understand as, "NPlus can't overlap poly that's used by a pmos if that poly is closer than 0.32um to the actual gate zone"


[2025-11-24 4:16 p.m.] 246tnt
But then I get this from the DRC. ( Only `COMP` / `Nplus` / `Poly` shown ). And the `Nplus` doesn't overlat `Poly` _at_ _all_ ...

{Attachments}
2025-11_media/2025-11-24_998x540_scrot-E94DC.png


[2025-11-25 2:45 a.m.] bailey8889
Started a thread.


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Exported 10 message(s)
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